Data processing systems typically accomplish the support of a variable number of human or process peripheral devices, including displays, keyboards and external data storage in the form of hard drive or other magnetic disc devices, through standardized I/O electrical channels commonly referred to as buses. The use of a peripheral bus as a common arrangement for connecting the peripheral devices or peripheral parts of a computer system to the processor has provided for system flexibility and has facilitated the adaptability of new peripheral devices and other system enhancements to existing computers. However, performance of these integrated computer systems is limited in one respect by the inability of the relatively simple, low cost peripheral bus to handle concurrent operations as the number of discrete peripherals and their functions increase. Overcommitment of the peripheral bus can lead to the exclusion of operation requests, overload and system failure. Systems in which many devices share a common bus therefore typically utilize schemes for allocating access to the bus under conditions during which a plurality of associated devices may concurrently request access. For example, see U.S. Pat. No. 4,817,037 entitled "Data Processing System With Overlap Bus Cycle Operations." A variety of priority arbitration schemes are known in the art. See IBM Technical Disclosure Bulletin, Vol. 17, No. 4, September 1974, entitled "Scheduling an Input/Output Channel Allowing for Committed and/or Uncommitted Device Allocation Requests" and IBM Technical Disclosure Bulletin, Vol. 26, No. 2, July 1983, entitled "Selective Processing Enablement for I/O Interruptions".
The function of controlling peripheral devices and allocating channel priority can place significant operational demand on a system, and especially where the speed of operation of the processor is greatly increased relative to that of the peripheral devices, overall efficiency of the data processing system may suffer. As a result, it has been preferred that these control functions be separated from the main processor and assigned to an input/output channel controller (IOCC) which provides the main control interface with the peripheral bus to which any number of different peripheral devices may be attached. The IOCC may be programmed with an appropriate priority arbitration scheme to allocate bus access in accordance with the priority criteria desired.
System efficiency is also greatly improved by giving the IOCC the ability to access memory autonomously without using processor instructions. Direct memory access (DMA) allows an input/output data path or channel to be established between the peripheral devices and system memory, whereby the processor can independently execute instructions or perform operations utilizing other portions of the system memory.
Channel or data buffers are included in the IOCC to enhance DMA performance when there is a mismatch between the amount of information that can be transmitted per cycle between the system memory and the IOCC across an internal bus, and the amount of information that can be transmitted between the IOCC and the peripheral devices across the peripheral bus. For example, an IOCC data buffer with four, one byte locations can be used to accumulate data one or two bytes at a time from a peripheral device over an 8/16-bit peripheral bus into thirty-two (32) bit wide quantities. The contents of the data buffer can then be transferred in a single DMA write, i.e. store, operation through a larger thirty-two (32) bit internal bus to the system memory. When performing DMA read, i.e. load operations from system memory to a peripheral, thirty two bits of information are fetched from the system memory into the data buffer in one operation through the internal bus. The data is then transferred from the buffer one or two bytes at a time to the peripheral device. By reducing the number of cycles or transactions necessary to transfer data between the system memory and the IOCC in both the read and write modes, the data buffer minimizes processor lockout that occurs to handle these transactions, thereby increasing the overall efficiency of the data processing system. More than one data buffer may be provided in the IOCC, each serving as a temporary data storage location for a separate peripheral device. The use of multiple data buffers generally is known and described in U.S. Pat. No. 3,699,530.
A problem associated with data transfer between multiple peripheral devices and system memory in a buffered DMA environment is that a transaction requiring movement of data across both the peripheral bus and the internal bus between the data buffers and the system memory by the IOCC is a relatively slow operation compared to the normal peripheral channel data operations taking place across the peripheral bus. The result is that any DMA transaction which requires a system memory access will be slower than one which operates completely out of the data buffers. The length of the transaction is increased by the need to perform two channel arbitrations; the first to gain control of the peripheral bus and the second to gain control of the internal bus. Valuable peripheral bus bandwidth is thereby wasted for DMA transactions that include a lengthy system memory operation on the data buffer while a faster transaction for a lower priority peripheral device must wait for access to the peripheral bus.
It is an object of the present invention to provide an improved data processing system in which direct memory access between a number of peripheral devices sharing a common peripheral bus and a system memory device is accomplished by an input/output channel controller (IOCC) having data buffers.
It is a further object of the present invention to provide a data processing system of the above type in which a method and apparatus is provided for enhancing DMA performance by optimizing the transaction availability of the peripheral bus.
It is a still further object of the present invention to provide a data processing system of the above type in which the established priority arbitration scheme for granting access to the peripheral bus among contending peripheral devices is conditioned according to the data status of the data buffer to be accessed.